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UCC2540
SLUS539 - JUNE 2004
HIGH EFFICIENCY SECONDARY SIDE SYNCHRONOUS BUCK PWM CONTROLLER
FEATURES D On-Chip Predictive Gate Drivet for D D D D D D D D D D
High-Efficiency Synchronous Buck Operation Dual 3-A TrueDrivet Outputs 1-MHz High Frequency Operation with 70-ns Delay from SYNCIN to G1 Output Leading Edge Modulation Overcurrent Protection using a Parallel Average Current Mode Control Loop 3 Modes to Support 2.7-V to 35-V Bias Operation Reverse Current Protection for Output Stage User Programmable Shutdown 1.0% Initial Tolerance Bandgap Reference High Bandwidth Error Amplifiers Thermally Enhanced HTSSOP 20-Pin PowerPADt Package
APPLICATIONS D Secondary-Side Post Regulation (SSPR) for D D
Multiple Output Power Supplies Cascaded Buck Converters Post Processing Converters for Bus Converter and DC Transformer Architectures
DESCRIPTION
The UCC2540 is a secondary-side synchronous buck PWM controller for high current and low output voltage applications. It can be used either as the local secondary-side controller for isolated dc-dc converters using two-stage cascaded topologies or as a secondary-side post regulator (SSPR) for multiple output power supplies. The UCC2540 runs with the synchronization signal from either the primary side or the high duty cycle quasi-dc output of bus converters or dc transformers. For higher efficiency, it also incorporates the Predictive Gate Drivet technology that virtually eliminates body diode conduction losses in synchronous rectifiers.
Main Output
SIMPLIFIED APPLICATION DIAGRAM
UCC25701 Input C1 FB OUT QP VFB UCC2540 13 VDRV VEA- 7 14 G2 12 G2S 16 VDD 19 BST 18 G1 20 SWS 17 SW 15 PGND 11 SS CEA- 8 RSET 1 R2 COMP 9 G2C 3 REF 2 TR 10 Main Output R1 RSNS
AUX Output
SYNCIN RAMP 5 4 UDG-04057
Predictive Gate Drive, TrueDrive, and PowerPAD, are a trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
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UCC2540
SLUS539 - JUNE 2004
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DESCRIPTION (CONT.)
The UCC2540 is available in the extended temperature range of -40C to 105C and is offered in thermally enhanced PowerPADt 20-pin HTSSOP (PWP) package. This space saving package with standard 20-pin TSSOP footprint has a drastically lower thermal resistance of 1.4C/W JC to accommodate the dual high-current drivers on board.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)(2)
UCC2540 Supply voltage range, VDD Supply current, IVDD VDD CEA-, COMP, G2C, RAMP, SS, TR, VEA- VDRV G1, BST Analog input voltages SW, SWS G2, G2S SYNCIN Sink current (peak), IOUT_SINK Source current (peak), IOUT_SOURCE Operating junction temperature range, TJ Storage temperature, Tstg G1, G2 G1, G2 36 50 -0.3 to 3.6 -0.3 to 9 SW-0.3 to SW+9 -1 to 36 -1 to 9 -0.3 to 8.0 3.5 -3.5 -55 to 150 -65 to 150 C C A V UNIT V mA
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal.
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, VDD Supply voltage, VDRV Supply voltage, REF Supply voltage bypass, CVDD Reference bypass capacitor, CREF VDRV bypas capacitor, CVDRV BST-SW bypass capacitor, CBST-SW Timer current resistor range, RRSET PWM ramp capacitor range, CRAMP Turn-off capacitor range, CG2C COMP pin load range, RLOAD Junction operating temperature, TJ Mode 1 Mode 2 Mode 3 8.5 4.75 3.0 1.0 0.1 0.2 0.1 10 100 120 6.5 -40 105 50 680 1000 pF k C k 3.3 2.2 1.0 2.2 F F TYP MAX 35 8.00 3.6 V UNIT
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UCC2540
SLUS539 - JUNE 2004
ORDERING INFORMATION
TA = TJ HTSSOP-20 (PWP)(1) Bulk
-40C to +105C UCC2540PWP (1) The PWP package is also available at 70 devices per tube and taped and reeled at 2,000 devices per reel. Add an R suffix to the device type (i.e., UCC2540PWPR). See the application section of the data sheet for PowerPAD drawing and layout information.
CONNECTION DIAGRAM
PWP PACKAGE (TOP VIEW)
RSET REF G2C SYNCIN RAMP GND VEA- CEA- COMP TR
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
SWS BST G1 SW VDD PGND G2 VDRV G2S SS
THERMAL INFORMATION
PACKAGE FAMILY PowerPAD HTSSOP-20 PACKAGE DESIGNATOR PWP JA (C/W) (with PowerPAD) 22.3 to 32.6 (500 to 0 LFM) JC (C/W) (without PowerPAD) 19.9 JC (C/W) (with PowerPAD) 1.4 MAXIMUM DIE TEMPERATURE 125C
ELECTRICAL CHARACTERISTICS
VDD = 12 V, 1-F capacitor from VDD to GND, 1-F capacitor from BST to SW, 1-F capacitor from REF to GND, 0.1-F and 2.2-F capacitors from VDRV to PGND, fSYNCIN = 200 kHz, TA = TJ = -40C to 105C, (unless otherwise noted). PARAMETER OVERALL DC IVDD Operating current fS = 200 kHz, MODE 1 MODE 1 MODE 1 MODE 2, MODE 2 MODE 2 MODE 3 MODE 3 MODE 3 VVDD= VVDRV= 2.7 V VVDD = 4 V CLOAD = 2.2 nF UNDERVOLTAGE LOCKOUT VVDD VVDD VVDD VVDRV VVDRV VVDRV VREF VREF Start threshold voltage Stop threshold voltage Hysteresis Start threshold voltage Stop threshold voltage Hysteresis Start threshold voltage Stop threshold voltage 8.0 7.5 0.3 4.30 4.0 0.15 2.75 2.25 0.3 8.5 8.0 0.5 4.65 4.3 0.35 3.00 2.50 0.5 9.0 8.5 0.8 4.85 4.6 0.55 3.20 2.70 0.8 V 8 9 11 12 13 30 mA TEST CONDITIONS MIN TYP MAX UNIT
VREF Hysteresis (3) Ensured by design. Not production tested.
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UCC2540
SLUS539 - JUNE 2004
ELECTRICAL CHARACTERISTICS
VDD = 12 V, 1-F capacitor from VDD to GND, 1-F capacitor from BST to SW, 1-F capacitor from REF to GND, 0.1-F and 2.2-F capacitors from VDRV to PGND, fSYNCIN = 200 kHz, TA = TJ = -40C to 105C, (unless otherwise noted) PARAMETER VOLTAGE REFERENCE (REF) VREF ISC Reference output voltage Short circuit current Line regulation Load regulation PWM (RAMP) DMIN VRAMP tDEAD IRAMP VCEA+ GBW Minimum duty cycle Offset voltage Timeout threshold voltage G1 deadtime at maximum duty cycle ratio Ramp charge current Offset voltage Gain bandwidth(3) ICOMP = 0 A, VVEA- = 2.0 V ICOMP = 200 A, VVEA- = 1 V ICOMP = 0 A, VVEA- = 1 V VCEA- = 3.3 V, VCEA- = 1.5 V VCEA- = 0 V, 0 2.2 60 -200 VCOMP = 1.0 V, VVEA- = 0 V VCEA- = 1.5 V, 0.35 0 ICOMP = VVEA-, VTR = 1.0 V, 0C TA 105C Total variation ICOMP = 0 A, VVEA- = 2.0 V, ICOMP = 200 A, VVEA- = 1 V, ICOMP = 0 A, VVEA- = 1 V VCEA- = 1.75 V, VCEA- = 0 V, VTR = 0 V VCEA- = 0 V 0 2.2 60 -300 VCOMP = 1.0 V, VVEA- = 1.5 V VCEA- = 0 V, 0.35 0.60 2.5 100 -150 0.80 VSS- = 1.5 V VCOMP = VVEA- 0.40 25 1.485 1.47 3 0.75 48 1.500 1.50 4 0.1 0.83 3.0 140 -50 1.70 dB A mA V 0.60 2.5 100 -80 0.80 fSYNC = 200 kHz RRSET = 10 k Total variation 0.10 2.3 150 -325 45 3 0.25 2.5 175 -300 50 4 0.1 V 0.83 3.0 140 -10 1.70 2 1.00 70 1.515 1.53 V MHz V dB nA mA V V mV 0% 0.45 2.8 200 -275 55 V ns A mV MHz TA = 25C Total variation VREF = 0 V, TA = 25C 5.25 V VREF 7.2 V 0 mA IREF 5 mA 3.28 3.2 10 0 0 3.30 3.3 13 1.5 30 3.32 3.4 20 15 70 mV V mA TEST CONDITIONS MIN TYP MAX UNIT
CURRENT ERROR AMPLIFIER
VOL
Low-level output voltage
VOH AVOL IBIAS ISINK CMR VSS_OFF VTR_OFF VVEA+ GBW
High-level output voltage Open loop Bias current Sink current Common mode input range(3) Offset voltage from soft-start input Offset voltage from tracking input Threshold voltage (from VEA- to COMP) Gain bandwidth(3)
VOLTAGE ERROR AMPLIFIER
VOL
Low-level output voltage
VOH AVOL IBIAS ISINK
High-level output voltage Open loop Bias current Sink current(4)
(3) Ensured by design. Not production tested.
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UCC2540
SLUS539 - JUNE 2004
ELECTRICAL CHARACTERISTICS
VDD = 12 V, 1-F capacitor from VDD to GND, 1-F capacitor from BST to SW, 1-F capacitor from REF to GND, 0.1-F and 2.2-F capacitors from VDRV to PGND, fSYNCIN = 200 kHz, TA = TJ = -40C to 105C, (unless otherwise noted) PARAMETER CURRENT SET IOUT VRSET Output current RRSET = 10 k -158 1.42 2.3 1.50 RRSET = 10 k RRSET = 10 k RRSET = 10 k -325 -230 50 0.35 VVDD = 8.5 V 9 V VVDD 35 V -5 mA IVDRV 0 mA 6.87 0 0 15 VSWS = 0 V VSWS = 0 V VG2S = 0 V VG2S = 0 V VG2S = 0 V VSWS = 0 V 1.90 1.00 -0.70 1.90 1.0 -1.8 -0.5 VSW = 0 V, VSW = 0 V, VSW = 0 V, VSW = 0 V, VBST = 6 V, VBST = 6 V, VBST = 6 V, VBST = 6 V, VG1 = 0.5 V VG1 = 5.7 V VG1 = 3.0 V VG1 = 3.0 V 0.3 10 -150 1.50 2.5 1.65 -300 -200 70 0.45 7.20 50 50 30 2.25 1.25 -0.50 2.25 1.2 -1.3 -0.3 0.7 25 3 -3 12 12 25 25 ns A -142 1.58 2.7 1.80 -275 -170 100 0.55 7.53 100 100 50 3.10 1.03 -0.37 2.90 1.3 -0.9 -0.1 1.3 45 V mA V V mA mV mA V A A V RSET voltage RRSET = 10 k SYNCHRONIZATION AND SHUTDOWN TIMER (SYNCIN, G2C) Timer threshold SYNCIN threshold ICHG(G2C) Shutdown timer charge current SOFT-START (SS) ICH(SS) IDSCH(SS) Charge current Discharge current Discharge/shutdown threshold DRIVE REGULATOR (VDRV) VVDRV Output voltage Line regulation Load regulation ISC Short-circuit current G2S GATE DRIVE SENSE G2S rising threshold voltage G2S falling threshold voltage IG2S Current SWS GATE DRIVE SENSE SWS rising threshold voltage SWS falling threshold voltage ISWS Current Negative threshold voltage G1 MAIN OUTPUT RSINK RSRC ISINK ISRCE tRISE tFALL Sink resistance Source resistance Sink current(3) Source current(3) Rise time Fall time V TEST CONDITIONS MIN TYP MAX UNIT
A A V
CLOAD = 2.2 nF, from G1 to SW CLOAD = 2.2 nF, from G1 to SW
(3) Ensured by design. Not production tested.
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UCC2540
SLUS539 - JUNE 2004
ELECTRICAL CHARACTERISTICS
VDD = 12 V, 1-F capacitor from VDD to GND, 1-F capacitor from BST to SW, 1-F capacitor from REF to GND, 0.1-F and 2.2-F capacitors from VDRV to PGND, fSYNCIN = 200 kHz, TA = TJ = -40C to 105C, (unless otherwise noted) PARAMETER G2 SYNCHRONOUS RECTIFIER OUTPUT RSINK ISINK ISRC tRISE tFALL Sink resistance Sink current(3) Source current(3) Rise time Fall time VG2 = 0.3 V VG2 = 3.25 V VG2 = 3.25 V CLOAD = 2.2 nF, from G2 to PGND CLOAD = 2.2 nF, from G2 to PGND VSW = GND 6.2 90 50 3.5 wrt G1 falling wrt G1 falling wrt G1 rising wrt G1 rising 5 15 3 -3 12 12 6.7 115 70 5.0 -24 62 -68 10 25 25 7.5 130 90 6.5 ns ns V A 30 TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage, G2 DEADTIME DELAY (see Figure 1) tON(G1) tOFF(G1) tON(G2) tOFF(G2) tON(G2) tON(G2) tOFF(G2) tOFF(G2) RAMP rising to G1 rising SYNCIN falling to G1 falling Delay control resolution G2 on-time minimum G2 on-time maximum G2 off-time minimum G2 off-time maximum
(3) Ensured by design. Not production tested. tOFF(G1) SYNCIN
VERR
RAMP G2C tON(G1) tON(G2) G1 tOFF(G2) G2
Figure 1. Predictive Gate Drive Timing Diagram
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UCC2540
SLUS539 - JUNE 2004
FUNCTIONAL BLOCK DIAGRAM
RSET 1 + - ISET 1.5 V VDD REF 2 VREF VREF REFERENCE VREF VDRV UVLO GLO PWR VDD 19 BST HIGH SIDE DRIVER 18 G1 20 SWS
G1D 17 SW G2 TIMER G2TO UVLO
G2C
3
GLO 2 x ISET G2 UVLO
G1D
SYNCIN 4 VREF
SYNC
100 ns CLK
DRIVE REGULATOR
16
VDD
15 PGND PREDICTIVE LOGIC PGND LOW SIDE DRIVER 14 G2
RAMP 5 GND 6
2 x ISET
RAMP RAMP & PWM LOGIC VERR
PWM BIAS PWR
VEA- 7 CEA- 8 9 ERROR AMPLIFIERS AND FAULT LOGIC
PGND VREF HUP 1.33 x ISET 13 VDRV
COMP
12 G2S 11 SS
TR 10 1.73 x ISET
UDG-04056
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UCC2540
SLUS539 - JUNE 2004
PIN ASSIGNMENTS
TERMINAL NAME BST CEA- COMP G1 G2 G2C G2S GND PGND RAMP REF(1) NO. 19 8 9 18 14 3 12 6 15 5 2 I/O I I I O O I I - - I I/O DESCRIPTION Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on time. Bypass BST to SW with an external capacitor. Inverting input of the current error amplifier used for output current regulation. Output of the voltage and current error amplifiers for compensation. High-side gate driver output that swings between SW and BST. Low-side gate driver output that swings between PGND and VDRV. Timer pin to turn off synchronous rectifier. The capacitor connected to this pin programs the maximum duration that G2 is allowed to stay HIGH. Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate deadtime. Ground for internal circuitry. GND and PGND should be tied to the pc-board ground plane with vias. Ground return for the G2 driver. Connect PGND to the pc-board ground plane with several vias. Input pin to connect capacitor to GND to generate the PWM ramp and serve as a maximum duty ratio timer. 3.3-V reference pin. All internal circuits are powered from this 3.3-V rail. Bypass this pin with at least 0.1 F of capacitance for REF loads that are 0 mA to -1 mA. Bypass this pin with at least 1 F of capacitance if it is used as an input (Mode 3) or if it has large or pulsating loads. Pin to program timer currents for G2C, RAMP, SS charge and SS discharge. This pin generates a current proportional to the value of the external resistor connected from RSET pin to GND. RSET range is 10 k to 50 k (giving a programmable nominal ISET range of 30 A to 150 A, respectively). Soft start and shutdown pin. Connect a capacitor to GND to set the soft-start time. Add switch to GND for immediate shutdown functionality. Input pin for timing signal. G1 driver return connection. Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain close to the MOSFET package. Tracking input to the voltage error amplifier. Power supply pin to the device and input to the internal VDRV drive regulator. Normal VDD range is from 4.5 V to 36 V. Bypass the pin with at least 1 F of capacitance. Output of the drive regulator and power supply pin for the G2 driver. VDRV is also the supply voltage for the internal logic and control circuitry.
RSET
1
I
SS SYNCIN SW SWS TR VDD VDRV
11 4 17 20 10 16 13
I I - I I I I
VEA- 7 I Inverting input of the voltage error amplifier used for output voltage regulation. (1) REF is an input in Mode 3 only.
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
The UCC2540 is a high-efficiency synchronous buck controller that can be used in many point-of-load applications. It can be used as a local controller for cascaded techniques such as post processing converters for isolated integrated bus converters (IBC) and dc transformer architectures. It can also be used as a general purpose secondary-side post regulator for high-accuracy multiple-output power supplies.
Using UCC2540 as the Secondary-Side PWM Controller in the Cascaded Push-Pull Buck Two Stage Converter
The two-stage cascaded push-pull buck topology converts higher-input bus voltage such as 48-V telecom voltage to sub 2-V output voltages.
Q2' T1 NS2 NS1 NP2 Q1' V1 C1 Q1 Q2 L1 Q3 V3 Q4 C2 UCC2540 VEA- 7 13 VDRV 14 G2 12 G2S 16 VDD 19 BST 18 G1 20 SWS OUT1 OUT2 SYNC UCC28089 11 SS SYNCIN RAMP 5 4 CLOCK RESET
UDG-02140
RSNS OUT1 RA
NP1 VIN 48-V
REF
2 R1
TR 10 COMP 9 G2C 3
RB
17 SW 15 PGND
CEA- 8 RSET 1 R2
Figure 2. Secondary-Side Controlled Cascaded Push-Pull/Buck Converter The primary-side power stage is an open loop push-pull converter that provides voltage step-down, and galvanic isolation. This takes the high bus voltage and converts it into an intermediate voltage such as 7 V. The primary-side push-pull gate drive signals can come from either off-the-shelf oscillators or a fully integrated 50% duty dual-output oscillator such as the UCC28089. The secondary-side power stage is a buck converter that is optimized for low-output voltage regulation. The clock reset pulse signal from the primary side is transmitted using a signal transformer.
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
There are many advantages to this secondary-side control circuit. The simple isolated power stage does not require any feedback across the isolation boundary. Since the primary-side oscillator is free running, there is no need for an isolated start-up power supply. This high-frequency circuit provides soft-switching operation (for all six MOSFET switches), optimum transformer core utilization, and minimizes filter requirements because there are no additional high-current inductors. The push-pull primary side permits simple direct drive control of the input stage MOSFETs. In exchange, it requires that the input MOSFETs are rated to at least twice the peak input line voltage. This configuration works well for 36-V to 72-V input line applications, because there are many suitable power MOSFETs available in the range of 150 V. For applications with larger input voltages, a half bridge or full bridge with alternating modulation might be more suitable for an input stage. Thus, the cascaded topology has a large degree of flexibility with input power stages. The cascaded topology also has flexibility in the output stages, as well. For additional information on this topology refer to Power Supply Seminar SEM-1300 Topic 1: Unique Cascaded Power Converter Topology for High Current Low Output Voltage Applications [1]. The topic discusses the operating principles, design trade-offs, and critical design procedure steps.
UCC2540 in Multiple Output Power Supplies
One such flexibility is an ability to easily add independently regulated auxiliary outputs. A multiple output implementation of the cascaded push-pull/buck power converter is shown in Figure 3.
Q2' L2
Q3 NP1 INPUT NP2 Q4
C2
OUT1
C1 Q1 Q2
Q1' PWM PWM
UCC2540 14 G2 18 G1 SYNCIN 4
OUT1
OUT2 SYNC
CLOCK RESET L3 Q5 Q6
SYNCIN
UCC28089
C3
OUT2
UCC2540 PWM2 PWM2 14 G2 18 G1 SYNCIN 4 SYNCIN
UDG-02142
Figure 3. Multiple Output Implementation of Push-Pull/Buck Cascaded Converter
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
Using UCC2540 as the Secondary-Side Post Regulator
UCC2540 can also be used as a secondary-side post regulator (SSPR) for precision regulation of the auxiliary voltages of multiple output power supplies, as shown in Figure 4. The UCC2540 uses leading-edge modulation so that it is compatible with either voltage-mode or current-mode primary-side control converters using any topology such as forward, half-bridge or push-pull.
Q2' L2
NP1
NP2 C2
MAIN OUTPUT
INPUT
C1 Q1 Q2
Q1' VFB L3 Q5 Q6 C3 AUX OUT1
OUT1 UCC3808x
OUT2 FB 1 PWM2 14 G2 PWM2 18 G1 SYNCIN 4
UDG-02145
UCC2540
Figure 4. Multiple Output Converter with Primary Side Push-Pull Converter
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
CEA- and VEA- pins: Current Limit and Hiccup Mode
Typical power supply load voltage versus load current is shown in Figure 5. This figure shows steady state operation for no-load to overcurrent shutdown (soft-start retry is not depicted in the diagram). During the voltage regulation conditions, the voltage error amplifier output is lower than the current error amplifier, allowing the voltage error amplifier to control operation. During the current limit conditions, the current error amplifier output is lower than the voltage error amplifier, allowing the current error amplifier to control operation. The boundary between voltage and current control occurs when the difference between CEA- and VEA- tries to exceed 50 mV. Current limiting begins to occur when the difference between CEA- and VEA- exceeds 50 mV. For currents that exceed this operating condition, the UCC2540 controls the converter to operate as a pure current source until the output voltage falls to half of its rated steady state level. Then the UCC2540 sets both G1 and G2 outputs to LOW and it latches a fault that discharges the soft-start voltage at 30% of its charging rate. The UCC2540 inhibits a retry until the soft-start voltage falls below 0.5 V. A functional diagram of the voltage and current error amplifiers is shown in Figure 6.
VLOAD - Load Voltage - V
VREG
Limited Current
Shutdown
ILOAD - Load Current - A
UDG-04053
Figure 5. Typical Power Supply Load Voltage vs Current
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
From Power MOSFET Switch Node RS C RLOAD TR RV1 SS 0.7 V + + + 1.5 V 50 mV CEA- 8 Current Error Amplifier + COMP + 9 + Voltage Error Amplifier 1.25 R R 1.5 V + VERR to Modulator Inverting Amplifier
RI1
VEA- 7
UCC2540 CFV ZFV
ZFV
RFV
ZIV
RFI
CFI CFIR ZIV
UDG-04052
RI2
RV2
Figure 6. Error Amplifier Configuration Component selection includes setting the voltage regulation threshold, then the current limit threshold, as described below. Voltage vs. Current Programming (refer to Figure 6): 1. Determine the ratio V LOAD(reg) V LOAD(reg) R V1 + *1V+ *1V R V2 V VEA* ) Threshold Voltage 1.5 V (typ) R V1 R V2 V CEA)offset voltage , where IS(max) is the current limit level, I S(max)
2. Sense resistor R S + 1 ) VCEA+offset = 50 mV (typ).
3. Arbitrarily select either RV1 or RV2 so that the smallest of the two resistors is between 6.5 k and 20 k. Then calculate the value of the other resistor using the equation in the first step. If the converter is in a current-limit condition and the output voltage falls below half of the regulated output voltage, the UCC2540 enters into a hiccup (restart-retry) mode. Figure 7 shows typical signals during hiccup mode.
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
SYNCIN 3.3 V SS 0.5 V
ILOAD
VLOAD RAMP
G2C
G1 G2
UDG-04046
Figure 7. Typical Hiccup Mode waveforms
COMP, VEA- and CEA- pins: Voltage and Current Error Amplifiers
From no-load to full rated load operating conditions, the UCC2540 operates as a voltage mode controller. Above the programmed rated current, there are two levels of over current protection; constant current limit and overcurrent reset/retry. This section gives suggestions on how to design the voltage controller and current controller so that they interact with one another in a stable fashion. Refer to the functional diagram of the voltage and current error amplifiers in Figure 6. The voltage error amplifier in the figure shows three non-inverting inputs. The lowest of the three non-inverting inputs (1.5 V, SS and TR) is summed with the non-inverting input to achieve the voltage error signal. The lowest of the two outputs drives the inverting stage which in turn, drives the modulator. During steady state voltage control operation, the feedback elements in the current loop have no effect on the loop stability. When current limit occurs, the voltage error amplifier effectively shuts OFF and the current error amplifier takes control. During steady state current limit operation, the negative feedback elements in the voltage error amplifier loop become positive feedback elements in the current error amplifier loop. In order for the current error amplifier to be stable, the impedances in the feedback path of the current error amplifier must be lower than the impedances in the feedback path of the voltage error amplifier. This means that resistors in the current error amplifier negative feedback path must be less than the resistors in the voltage error amplifier negative feedback path. Also capacitors in the current error amplifier negative feedback path must be larger than capacitors in the negative feedback path of the voltage error amplifier negative feedback path. (Capacitance is really an admittance value rather than an impedance value). This concept is illustrated in Figure 6. In order for the current loop to be stable in Figure 6, ||ZIV|| must be less than ||ZFV|| over all frequencies. This can be achieved if RFI < RFV and CFI > CFV.
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
Another issue that can occur during current limit operation is modulator stability. In order for the modulator to be stable, the rising slope of the current ripple measured at the COMP pin must be smaller than the rising slope that is measured at the RAMP pin. This can be met either in the selection of the ratio of ||ZIV|| to ||ZFV||, or by the addition of a capacitor in parallel to RFI and CFI, such as CFIR, in Figure 6. Stable Dynamic Current Loop Design (refer to Figure 6): 1. Using any favorite approach, design the voltage error amplifier for stable voltage mode design. Use at least 15 k for any resistors in the negative feedback path of the voltage error amplifier (between pins 9 and 7). This does not apply to resistance values between the power supply output voltage and pin 7; it also does not apply to resistance values between ground and pin 7. 2. The goal is to design the current limit control loop so that it drives the converter to maintain 50 mV between the VEA- pin and the CEA- pin during current-limit conditions. Select the current sense element and the voltage divider ratios for the VEA- pin to ground and the CEA- pin to ground to provide the desired current limit level. 3. Place the same configuration of components in the negative feedback path of the current error amplifier (between pins 9 and 8), that are in the negative feedback path of the voltage error amplifier (between pins 9 and 7). However, use resistors with values that are 67% of the corresponding resistors that are between pins 9 and 7 and use capacitors that are 150% of the corresponding capacitors that are between pin 9 and pin 7. 4. Check the COMP signal. If it is unstable, place a capacitor (or increase the capacitance) between pins 9 and 8 in order to attenuate the current ripple. Raise the value of the capacitor until the COMP pin voltage becomes stable. Compare the COMP voltage with the RAMP voltage. With stable operation, the rising slope of the COMP voltage ripple is less than the rising slope of the RAMP pin.
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
RSET, RAMP, G2C, SS pins: Programming the Timer Currents
Set the base current to the timers with a resistor between RSET and GND. The block diagram of the UCC2540 shows the interaction of the RSET pin and the dependent current sources for the RAMP, G2C and SS features. The RSET pin is a voltage source; the current of the RSET pin is reflected and multiplied by a gain and distributed to the RAMP (gain = 2), G2C (gain = 2) and SS (charge gain = 1.33, net discharge gain = 0.4). The resistance applied to the RSET pin and GND should be in the range of 10 k < RRSET < 50 k. RAMP, G2C and SS timers are programmed by the selection of capacitors tied between each of their respective pins and GND.
G2C pin: G2 Timer
G2C Latch S Q G2TO
G2C 3 CG2C GLO G2
2 y IRSET 2.5 V
G2 Timeout Comparator *G1D +
RD Q
UVLO
*G1 with delay, but not blanked
UDG-04047
Figure 8. Functional diagram of the G2 Timer The G2C pin programs the maximum duration of the synchronous rectifier to facilitate low or zero duty ratio operation. FIgure 8 shows the functional diagram. This function is programmed by connecting a capacitor between the G2C pin and GND. The capacitor on G2C should be slightly larger than the capacitor on the RAMP pin. For best results, program the typical G2 time limit to be between 1.5 and 3 times the switching period (T). Notice that when the G2 timer reaches its limit, both G1 and G2 are forced to a LOW output. This feature prevents the current in the output inductor from excessive negative excursions during zero-duty ratio conditions. Program the G2 time-out (G2TO) duration using equation (1): C G2C + where 2 V RSET R RSET G2 Timeout Duration , Farads G2C Timer Threshold
(1)
D VRSET = 1.5 V(typ) D 1.5 T < G2 Timeout Duration < 3TS D G2C Timer Threshold = 2.5 V (typ)
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
RAMP pin: PWM Modulator and G1 Timer
The RAMP pin serves two purposes: (1) programming the gain of the PWM modulator and (2) programming the time-out duration of G1 in case the main power stage has not caused a SYNC pulse to occur. A diagram of the PWM modulator and G1 timer is shown in Figure 9. The UCC2540 has a leading edge modulator that compares the error output with the RAMP voltage. The modulator frequency is externally driven through the SYNCIN pin. The RAMP pin provides both a sawtooth wave for the PWM comparator and it functions as G1 time-out protection that is programmed by RSET and the value of the RAMP capacitor. A switching cycle begins with the falling edge of the SYNCIN signal, which must be LOW for at least 50 nanoseconds. The falling edge of SYNCIN generates a 100 ns discharge strobe (CLK), to the RAMP function and then, allows the RAMP capacitor to charge from the 2 x IRSET current source.
2 y IRSET RAMP 5
VERR +
PWM Comparator
PWM Latch S Q PWM
250 mV ENA 2.5 V + G1 Timeout Comparator CLK
Figure 9. PWM Modulator and G1 Time-Out Comparator Low-line or brownout conditions can cause the primary side duty ratio to approach 100% where parasitic converter impedances may temporarily impair the quality of the SYNCIN pulse. The RAMP timing function terminates the G1 pulse when the RAMP voltage exceeds 2.5 V. The duration of the RAMP timing function should be set as follows: 2 C RAMP w where V RSET R RSET TS (2)
PWM RAMP timeout threshold voltage
+
RD Q
UDG-04048
D TS = switching period D VRSET = 1.5 (typ) D PWM(RAMP) = 2.5 V (typ)
R SETC RAMP w 1.2 a Gain (PWM modulator) w 0.4 fS (3)
In order to use the G1 Timer feature, the peak RAMP voltage at the end of a switch cycle should be as close to 2.5 V as the CRAMP and RRSET tolerances allow. In other words, the PWM modulator gain should be programmed to be equal to, or slightly greater than 0.4 inverse-V.
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17
UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
SYNCIN pin
A falling edge applied to the SYNCIN pin generates a narrow pulse that is the base timer for internal UCC2540 functions. The SYNCIN pulse must be HI for at least 100 ns preceding the falling edge and LOW for at least 50 ns in order to be registered as a valid pulse. Due to the critical nature of the timing, avoid filtering the falling edge of the SYNCIN signal in order to avoid signal delay. The peak SYNCIN voltage can easily range from between 2.5 V and 6.6 V, which allows a simple resistive divider to scale the secondary transformer voltage in post regulator applications. Situations where the line voltage varies more extensively or there is extensive ringing may call for clamping and/or additional gain. Ground Clamping In applications where a ring or a spike causes SYNCIN to fall below GND, protect the pin with a Schottky diode (cathode = SYNCIN, anode = GND). Overvoltage Clamping The SYNCIN signal may require overvoltage clamping in applications where the peak SYNCIN voltage is perilously close to the absolute maximum level of 8 V, due to either ringing or voltage levels. The REF or VDRV can be used as clamp voltages, as in Figure 10. Make sure that REF or VDRV always sources current. The reason is that both REF and VDRV are used to detect the mode of operation when they are back-driven and they could latch into the wrong operating mode at start-up.
Main Output + RSR UCC2540 2 REF RRF 1 F G1 18 Auxiliary Output
4 SYNCIN G2 14 RSY
UDG-04049
Figure 10. REF Clamp for SYNCIN. Note the REF Load Resistor.
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
Another overvoltage clamping option is to directly clamp the SYNCIN pin. Unfortunately, Zener diodes have excessive junction capacitance which causes too much delay in the signal. However, a base-emitter clamp that achieves the desired clamping action can be employed with minimal delay to the SYNCIN signal. See Figure 11. Simply select RSR and (RCB + RBE) to give the appropriate 0 V to 3.3 V signal at low-line conditions. Then, select the ratio of RCB to RBE to cause the transistor to turn-on when SYNCIN exceeds 4 V.
Main Output + RSR 4 SYNCIN RCB G2 14 RBE
UDG-04050
UCC2540 G1 18 Auxiliary Output
Figure 11. VBE Clamp for SYNCIN SYNCIN Clamping for the Isolated Cascaded Buck Topology The UCC2540 is ideally suited as a secondary side controller for the cascaded buck topology, when it is partnered with the UCC28089 primary side start-up controller. The primary side controller transmits a pulse edge during its dead time. The UCC2540 uses the primary-side pulse in order to provide zero voltage conditions for primary- and secondary-side switches. The predictive delay feature tunes the secondary-side transition to minimize reverse recovery losses in the synchronous rectifier. The pulse-edge information can vary with the primary side bias voltage and therefore, it must be clamped. The circuit shown in Figure 12 includes the appropriate pulse-edge shaping circuit, clamping and 1500-V isolation. The recommended transformer, COEV part # MGBBT-00011-01, is smaller than many opto-isolators.
Primary Ground UCC28089 C1 R1 634 680 pF RCB L1 15 H RBE GND T1 1:1 SYNCIN
UDG-04051
Secondary Ground UCC2540 REF
SYNC
QCL 2N3904
Figure 12. Isolation and Clamping the SYNCIN Signal for Cascaded Buck Converters
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19
UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
VDD, VDRV, VREF and BST pins: Modes of Operation
Depending on the available bias voltage for the UCC2540, the startup, shutdown, and restart conditions are different. There are three distinct configurations or modes of biasing the UCC2540. The mode is detected and latched into an internal register during power-up when VREF crosses 2 V. The register is cleared when VDD, VDRV and VREF are simultaneously less than 1 V. All modes are compatible with either cascaded buck or with secondary-side post regulator (SSPR) topologies. The main bias voltage of Modes 1 and 2 can be implemented with a diode and a capacitor from an ac-voltage such as the secondary winding of the transformer. A summary of the modes and their programming requirements are listed in Table 1. Table 1. Modes and Programming Requirements
Mode 1 2 3 VBIAS Range (V) 8.5 to 36 4.75 to 8.5 3.0 to 3.6 Bias Pin VDD [16] VDRV [13] VREF [2] UVLO ON (V) VVDD = 8.5 UVLO OFF (V) VVDD = 8.0 Mode Requirement at Power-Up and VVREF = 2 V V VDD u V VDRV and V REF Remarks Widest line operation
VVDRV = 4.65 VVDRV = 4.3 V VDRV u V VDD and V REF VREF = 3.0 VREF= 2.5 V REF u V VDD and V VDRV Needs regulated bias and low VTH power MOSFETs
D Mode 1, or normal operation requires the availability of a bias of 8.5 V or higher for the device. Here, the
bias drives the VDD pin. The low-side drive bias, VVDRV = 7 V, is generated from an internal linear regulator and it directly draws current from the VDD pin. The high-side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin, when G2 is HI, via a diode between G2 and BST. The UCC2540 operates in Mode 1 if VVDD > (VVDRV and VVREF) when VVREF rises above 2 V. Mode 1 permits the widest range of bias voltages, operational from 8.5 V < VVDD < 35 V. This mode is compatible with systems that have a 12 VDC bias supply already available. Alternatively, Mode 1 is particularly useful for applications where the input line voltage varies over a wide range and the bias is to be derived directly from the reflected line voltage, such as in Fig. 13.
D Mode 2 is suitable for applications where the bias is typically 5 V (between 4.5 V and 8.0 V). The bias
voltage is applied to the VDRV terminal of the UCC2540. The high-side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin, when G2 is HI. Bias voltage to the VDD pin is obtained through an external voltage-doubler charge pump. If the system uses low threshold voltage power MOSFETs, VDD can be directly tied to the VDRV pin. The bias voltage could be either a bus converter output or an auxiliary supply, or the reflected converter input voltage that originates from a regulated source.
D Mode 3 is for synchronous buck converter applications where the bias voltage is a regulated 3.3-V source.
This is a common main output voltage in multiple output power converters. The bias voltage is applied to the VREF pin of the UCC2540. The UCC2540 operates in Mode 3 if it detects (VVREF > VVDRV and VDD) when VVREF rises above 2 V. Assorted combinations of modes and biasing schemes are shown in Figure 13 through Figure 18. In Mode 1 and Mode 2, the bias voltage can either be an independent auxiliary supply or it can be generated by rectifying and filtering the reflected line voltage, as shown in Figure 13 through Figure 16. A regulated auxiliary supply must be used with Mode 3 because the tolerance of the VREF voltage is the control tolerance of the UCC2540. In Mode 3, the regulated auxiliary supply can be independent of the power supply input voltage (as shown in Figure 18) or, the regulated auxiliary supply can be the same source as the power supply input voltage.
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
UCC2540 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High-Side Driver Predictive Logic Low-Side Driver SWS SW G2 G2S PGND D2 16 13 2 19 18 C1 20 17 14 12 15
UDG-04038
Rectified Bias 8.5 V VVDD 35 V Vin 0V 8.5 V VIN 35 V
C2
C3
C4
Q1
D1 Q2
Figure 13. Mode 1 With Rectified Biasing for Input Voltages Between 8.5 V and 35 V
UCC2540 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High-Side Driver Predictive Logic Low-Side Driver SWS SW G2 G2S PGND AUX Bias 8.5 V VVDD 35 V
16 13 2 19 18 C1 20 17 14 12 15 D1
0 V VIN 35 V Vin C2 C3 C4 0V Q1
Q2
UDG-04039
Figure 14. Mode 1 With Auxiliary Biasing for Bias Voltages Between 8.5 V and 35 V
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21
UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
UCC2540 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High-Side Driver Predictive Logic Low-Side Driver SWS SW G2 G2S PGND D2 D4 D3 Vin 0V C2 C1 20 17 14 12 15
UDG-04040
16 13 2 19 18
Rectified Bias 4.75 V VVDRV 8.0 V
C3
C4
C5
Q1
D1 Q2
Figure 15. Mode 2 With Rectified Biasing for Input Voltages Between 4.75 V and 8.0 V
UCC2540 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High-Side Driver Predictive Logic Low-Side Driver SWS SW G2 G2S PGND D2 AUX Bias 4.75 V VVDRV 8.0 V
16 13 2 19 18 C1 20 17 14 12 15 D1 C2 C3 C4
D3 0 V VIN 35 V C5 Q1 Vin 0V
Q2
UDG-04041
Figure 16. Mode 2 With Auxiliary Biasing for Bias Voltages Between 4.75 V and 8.0 V
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
UCC2540 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High-Side Driver Predictive Logic Low-Side Driver SWS SW G2 G2S PGND AUX Bias 4.75 V VVDRV 8.0 V 16 13 2 19 18 C1 20 17 14 12 15
UDG-04042
0 V VIN 35 V Vin C2 C3 C4 0V Q1 (Low VTH)
D1 Q2 (Low VTH)
Figure 17. Mode 2 With Auxiliary Biasing for Bias Voltages Between 4.75 V and 8.0 V and Low Threshold Power MOSFET Transistors
UCC2540 Drive (7.2 V) Regulator VDD VDRV VREF (3.3 V) Regulator VREF BST G1 High-Side Driver Predictive Logic Low-Side Driver SWS SW G2 G2S PGND D2 D3 Regulated 3.3-VDC Bias 4.75 V VVDRV 8.0 V
16 13 2 19 18 C1 20 17 14 12 15 D1
DC or Pulse Train 1.8 V VIN 5 V
C2
C4
C5
Q1 (Low VTH)
Q2 (Low VTH)
UDG-04043
Figure 18. Mode 3 With Regulated 3.3-VDC Bias
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23
UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
Charge Pump Capacitor Selection
Capacitors C1 through C5 are all part of a charge distribution network that allows the UCC2540 to pass charge to the MOSFET gates of Q1 and Q2 (all reference designators in this section refer to the schematics in Figure 13 through Figure 18). This section gives guidelines on selecting the values of C1 through C5 so that the converter functions properly. Specific capacitor values may need to be larger than the recommended value due to MOSFET characteristics, diode D1 - D4 characteristics and closed-loop converter performance. All three modes of operation require a charge pump capacitor and diode, C1 and D1, in order to drive the high-side power MOSFET. Modes 2 and 3 require additional charge pump capacitors and diodes in order to supply voltage to VDD. In general, all charge pump diodes should be Schottky diodes in order to have low forward voltage and high speed. The charge pump capacitors should be ceramic capacitors with low effective series resistance (ESR), such as X5R or X7R capacitors. The value of the charge pump capacitor C1 depends on the power MOSFET gate charge and capacitance, the voltage level of the Miller plateau threshold, the forward drop of D1 and the closed-loop response time. The unloaded high-side gate driver typically draws 2 nC of charge per rising edge plus 30 A of direct current from C1. Usually, the unloaded high-side gate driver load is miniscule compared to the gate charge requirements of the high-side power MOSFET, Q1. Typical values for C1 are approximately 50 to 100 times the input capacitance (CISS) of MOSFET Q1. This usually allows for transient operation at extremely large duty ratio, where C1 does not have sufficient time to fully recharge. If C1 is excessively large, its ESR and ESL prevents it from recharging during transients, including the start-up transient. Capacitors C2 through C5 are then selected based on the direction of charge transfer and the requirements of the UCC2540. Selection guidelines are shown in Table 2. Keep in mind that each converter design may require adjustments for larger capacitor ratios than those that are suggested in Table 2. The selection process begins at the left side of Table 2 and progresses towards the right side of the table, which is the reverse order of the charge flow during the first few cycles of start-up. If iteration is required in the design process, review the progression of the capacitors in the order from left to right that is shown in the table. Table 2. Charge Pump and Bias Capacitor Selection Guidelines
Mode 1 2 3 High-Side Drive Capacitor ( 0.1 F) C1 > 50 CISS C1 > 50 CISS C1 > 50 CISS VDRV Filter Capacitor C3 > 2 x C1 C3 > 2 x C1 C4 > 1 F 2 x C1 VREF Filter Capacitor C2 > 0.1 F C2 > 0.1 F C2 > 1.0 F VDD Filter Capacitor C4 > 1 F C4 > 1 F, 2 x C3 C4 > 1 F, 2 x C1 VDD Charging Capacitor n/a C5 > 2 x C4 C5 > 2 x C4
For Modes 2 and 3, the VDD filter capacitor, C4, in Table 2 must supply the IVDD idle current to the UCC2540 (approximately 11 mA) plus the charge to drive the gates G1 and G2. Capacitor C4 must be large enough to sustain adequate operating voltages during start-ups and other transients under the full operational IVDD current. Knowing the operating frequency and the MOSFET gate charges (QG), the average IVDD current can be estimated as: I VDD + I VDD(idle) ) Q G1 ) Q G2 fS (4)
D where fS is switching frequency
In order to prevent noise problems, C4 must be at least 1 F. Furthermore, it needs to be large enough to pass charge along to the power MOSFET gates. Thus C4 often needs to have at least twice the capacitance of the VDRV filter capacitor, as shown in Table 2.
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
Output Stage
The UCC2540 includes dual gate drive outputs and each is capable of 3-A peak current. The pull-up/ pull-down circuits of the driver are bipolar and MOSFET transistors in parallel. High-side and low-side dual drivers provide a true 3-A high-current capability at the MOSFET's Miller Plateau switching region where it is most needed. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. The output drivers can switch from VDD to GND. Each output stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external-schottky-clamp diodes are not required. The outputs are also designed to withstand 500-mA reverse current without either damage to the device or logic upset. For additional information on drive current requirements at MOSFET's Miller plateau region, refer to the Power Supply Seminar SEM-1400[2] and the UCC37323/4/5 datasheet[3].
Predictive Gate DriveTM Technology
The Predictive Gate Drive technology maximizes efficiency by minimizing body diode conduction. It utilizes a digital feedback system to detect body diode conduction, and adjusts the deadtime delays to minimize the conduction time interval. This closed loop system virtually eliminates body diode conduction while adjusting for different MOSFETs, temperature, and load dependent delays. Since the power dissipation is minimized, a higher switching frequency can be utilized, allowing for a smaller component size. Precise gate timing at the nanosecond level reduces the reverse recovery time of the synchronous rectifier MOSFET body diode, which reduces reverse recovery losses seen in the main (high-side) MOSFET. Finally, lower power dissipation reduction results in increased reliability.
19 BST 18 G1
17 SW Predictive Logic VDRV 14 G2 15 PGND
UDG-02149
20 SWS 12 G2S
Figure 19. For additional information on Predictive Gate Drive control and efficiency comparisons to earlier adaptive delay and adaptive control techniques, refer to the UCC27223 datasheet [3].
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25
UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
VDD and IDD
Although quiescent VDD current is low, total supply current is higher, depending on output gate drive requirements and the programmed oscillator frequency. Total VDD current (IVDD) is the sum of quiescent VDD current and the average output currents of G1 and G2, as described in equation (3). Knowing the operating frequency and the MOSFET gate charge (QG), average driver output current, per gate, can be calculated from: IG + QG where fS (5)
D fS is switching frequency
To prevent noise problems, connect a 1-F ceramic capacitor between the VDD and GND pins. Place the 1-F ceramic capacitor as close to the UCC2540 as possible. This capacitor is in addition to any electrolytic energy storage capacitors that may be used in the bias supply design.
Soft-Start and Tracking Features
Separate pins are provided for the soft-start feature and the tracking feature. Soft-start or tracking (sequencing) can be easily implemented with this configuration using a minimum number of external components. During a power-up transient, the converter output tracks the lower of the SS voltage, the TR voltage or a 1.5-V internal reference, provided the system is not in current limit. In other words, the voltage control loop is closed during power-up, provided the system is not current limited. Figure 20 shows the UCC2540 configured for soft-start operation. For applications that do not use the tracking feature, connect the TR pin to either SS or REF, as shown in the figure. Remote shutdown and sequential power-up can be easily implemented as a transistor switch across CSS.
TR
UCC2540 10 REF (3.3 V)
1.33y IRSET
Voltage
SS 11
CSS
Error
1.5 V
0.7 V
+ + +
Amplifier COMP
1.73 y IRSET
+
UVLO
VEA-
HUP
50 mV To Positive Input of Current Error Amplifier
UDG-04045
+
7
Figure 20. Using the Soft-Start Feature
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
The soft-start interval begins when the UCC2540 recognizes that the appropriate voltage (see Mode 1, 2 or 3) is above the UVLO level. The voltage of CSS then linearly increases until it is clamped at the REF voltage of 3.3V. Regulation should be reached when the soft-start voltage reaches about 2.2 V (1.5 V plus a diode drop). Select a CSS capacitor value using equation (5) to program a desired soft-start duration, tSS. C SS + 1.33 V RSET R SET Dt SS + 1.33 DV SS 1.5 V R SET Dt SS Farads 2.2 V
(6)
If a UVLO fault is encountered, both outputs of the UCC2540 are disabled and the soft-start pin (SS) is discharged to GND. The UCC2540 does not retry until the UVLO fault is cleared. Using the TR pin, the UCC2540 can be programmed to track another converter output voltage. If the voltage to be tracked is between 0 V and 3.3 V, simply connect the TR pin to the voltage to be tracked with a resistor that is approximately equal to the DC impedance that is connected to the VEA- terminal (RV1 || RV2, in Figure 6). If the voltage is above that range, use a voltage divider, again with an equivalent resistance that approximately equals the DC impedance that is connected to the VEA- terminal. Other strategies can be used to achieve sequential, ratiometric or simultaneous power supply tracking[14]. An implementation of sequential sequencing of a multiple output power supply[5] is shown in Figure 21. Applications where the loads include a processor with a core voltage of 1.5 V and I/O ports that require 3.3 V can require sequential sequencing in order to resolve system level bus contention problems during start-up. In this circumstance the core must power-up first, then after an initialization period of 130 ms, the ports are allowed to power-up.
From Transformer Secondary UCC2540 TR TPS3103K33 RESET VDD GND PFO MR PFI 1 k UCC2540 10 k REF TR SS CSS G1 G2 Core 1.5 V CSS 1.6 k SS G1 G2 5V 0V I/O 3.3 V
UDG-04061
Figure 21. Sequencing a Multiple Output Post Regulated Power Supply
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27
UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
Regulation loss due to loss of primary line voltage
130 ms V - Voltage - V 3.3
VI/O
1.5 1.43
VCORE
0 t - Time
UDG-04061
Figure 22. Using the TR pin, the UCC2540 can be programmed to ratio-metrically track another converter output voltage[5]. Ratio-metric tracking is when the ratio of the output voltages is constant from zero volts to the point where one or more of the outputs lock into regulation. The TR pin is easier to use for tracking than the SS pin because the external currents that would be applied to the SS pin may interfere with SS discharge currents and fault recovery. It should be understood that the voltage that is being tracked must lag the bias voltages (VDD, VDRV and REF) on start-up and lead the bias voltages during shutdown. Furthermore, the output that is being tracked must not reach its steady state DC level before the output that is tracking reaches its steady state DC level. Figure 23 illustrates the concept of programming an output voltage VC, to ratio-metrically track another output, VM.
VM (Leader) Main Power Supply (Leader) + VM MC VM (Leader) MM VC (Tracker) (a) ratio-metric sequencing
MM Core Power Supply (Trader) UCC2540 7 TR + VC MC
(b) simultaneous sequencing
VC (Tracker)
VM (Leader) AT ^ MC MM MM VC (Tracker) MC
(c) ratio-metric sequencing
UDG-04061
Tracking Ratio
Figure 23. Ratio-Metric Tracking
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UCC2540
SLUS539 - JUNE 2004
APPLICATION INFORMATION
The general circuit to program the UCC2540 to track the leader supply voltage by the tracking ratio AT is shown in Figure 24. To program the tracking profile gains GT1 and GT2, follow the ratio-metric tracking design procedure that is listed below. The special case of simultaneous sequencing for VM > 1.5V is the simplest to design; set RT1= RV1 and RT2= RV2, GT2 is not needed. In many other cases, the circuit can be simplified with the removal of the operational amplifier for GT2 and the Zener clamping diode. If an operational amplifier is necessary, it should be capable of rail to rail operation and usually low voltage bias; the TLV271 is an inexpensive solution for both of those requirements. Notice that the tracking circuit in Figure 24 also has a soft-start capacitor, CSS. The soft-start capacitor is useful for limiting the time between short-circuit retry attempts and it can prevent overshoot when recovering from a fault that is experienced in only the tracking supply but not the main supply.
Ratio-Metric Tracking Design Procedure (see Figures 21 and 22)
1. Determine the tracking ratio, AT. AT + MC MM
(7)
where MC and MM are the soft-start slopes of VC and VM, respectively. 2. Determine GV. GV + R V2 R V1 ) R V2 (8)
where RV2 and RV1are selected when designing the voltage control loop. 3. Test GT2 if necessary when VM 1.5 V or ATGV > 1. a. If GT2 is needed, set GT2 so that both equations (8) and (9) apply. G T2 + 1 ) R F1 R F2 (9)
so that both of the following apply: G T2 + 1.5 V V M G T1 and G T2 u A T GV
(10)
b. If GT2 is not needed, set GT2 = 1. 4. Set GT1 . G T1 + AT GV R T2 + R T1 ) R T2 G T2
(11)
5. Select RT1 and RT2 so that RT1 || RT2 RV1 || RV2 to minimize offset differences.
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29
UCC2540
SLUS539 - JUNE 2004
RF2
RF1
G T2 + 1 )
R F1 R F2
TLV271
+
Use GT2 stage if ATGV > 1 OR if VMGT1 1.5 V at steady-state
Main Power Supply (Leader)
+ VM
Rectified Secondary Voltage RT1 UCC2540 TR RT2 G T1 + R T2 R T1 ) R T2 *DZ 3.3 V SS CSS VEA- G2 G1 nVIN 0V + VC
RV1 RV2
GV +
R V2 R V1 ) R V2
UDG-04059
*DZ needed only if VMGT1GT2 > 3 V
Determined by voltage loop design
Figure 24. Programming the UCC2540 to Track Another Output More elaborate power supply sequencing and tracking can easily be implemented by extending the above techniques. Consult reference [5] for further information
THERMAL INFORMATION
The useful temperature range of a controller that contains high-current output drivers is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC2540 is available in the 20-pin HTSSOP PowerPADt package. The PowerPADTM HTSSOP-20 (PWP) offers the most effective means of removing the heat from the semiconductor junction and therefore long term reliability improvement. As illustrated in [5], the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the device package, reducing the jc down to 2C/W. Data is presented in [5] to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in [6] to realize a significant improvement in heat-sinking over standard non-PowerPAD surface mount packages.
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UCC2540
SLUS539 - JUNE 2004
TYPICAL CHARACTERISTICS
OUTPUT REFERENCE VOLTAGE vs TEMPERATURE
3.40 -275 RRSET = 10 k
RAMP CURRENT vs TEMPERATURE
VVREF - Reference Voltage - V
-285 3.35 IRAMP - Ramp Current - A
-295
3.30
-305
3.25
-315
3.20 -50
0
50
100
150
-325 -50
0
50
100
150
TJ - Junction Temperature - C
TJ - Junction Temperature - C
Figure 25
Figure 26
1.1
IG2C/IRAMP AND ISS/IRAMP vs TEMPERATURE
IG2C/IRAMP, RRSET =10k
7.6
REGULATOR OUTPUT VOLTAGE vs TEMPERATURE
MODE 1
1.0 IG2C/IRAMP, RRSET =50k 0.9 A/A
VVDRV - Regulator Output Voltage - V
7.4
0.8 ISS/IRAMP, RRSET =10k 0.7 ISS/IRAMP, RRSET =50k 0.6
7.2
7.0
0.5 -50
0 50 100 TJ - Junction Temperature - C
150
6.8 -50
0
50
100
150
TJ - Junction Temperature - C
Figure 27
Figure 28
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31
UCC2540
SLUS539 - JUNE 2004
TYPICAL CHARACTERISTICS
TRACKING TO VOLTAGE ERROR AMPLIFIER OFFSET vs TEMPERATURE
VCEA- - Current Error Amplifier Offset Voltage - mV 70
55
CURRENT ERROR AMPLIFIER OFFSET vs TEMPERATURE
60 VTR(OS) - Offset Voltage - mV
53
50
40
51
30
49
20
47
10
0 -50
0 50 100 TJ - Junction Temperature - C
150
45 -50
0
50
100
150
TJ - Junction Temperature - C
Figure 29
Figure 30
1.80
SYNCIN THRESHOLD VOLTAGE vs TEMPERATURE
5
INVERTING AMPLIFIER GAIN AND PHASE vs FREQUENCY
0
VSYNCHIN - Timing Signal Voltage - V
1.75
0 Phase Gain -10
-45
1.70 Gain - dB
-5
-90 Phase -
1.65
-135
1.60
-15
-180
-20 1.55 -25 1k 0 50 100 TJ - Junction Temperature - C 150
-225
1.50 -50
10 k
100 k
1M
10 M
-270 100 M
f - Frequency - Hz
Figure 31
Figure 32
32
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UCC2540
SLUS539 - JUNE 2004
TYPICAL CHARACTERISTICS
CURRRENT ERROR AMPLIFIER GAIN AND PHASE vs FREQUENCY
120 100 Gain 80 60 Phase - 40 20 0 -20 -40 1 10 100 1k -180 10 k 100 k 1 M 10 M 100 M Phase -135 -90 -45 0
VOLTAGE ERROR AMPLIFIER GAIN AND PHASE vs FREQUENCY
120 100 Gain 80 60 40 20 0 -20 -40 1 10 100 1k -180 10 k 100 k 1 M 10 M 100 M Phase -135 -90 -45 Phase - 33 0
Gain - dB
f - Frequency - Hz
Gain - dB
f - Frequency - Hz
Figure 33
Figure 34
OPERATING CURRENT (DC) vs BIAS VOLTAGE
12
10 IVDD - Bias Current - mA
8
6
4
2
0 0 5 10 15 20 25 30 VVDD - Bias Voltage - V 35 40
Figure 35
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UCC2540
SLUS539 - JUNE 2004
TYPICAL CHARACTERISTICS
G2 Lower Gate Drive (5V/div) Predictive Delay Adjustment G2 Lower Gate Drive (5V/div)
SW Node (500 mV/div)
SW Node (5V/div)
Synchronous FET Body Diode Conduction t - Time - 20 ns/div
t - Time - 20 ns/div
Figure 36. Predictive Gate Drive - G2 Falling
Figure 37. Predictive Gate Drive - G2 Falling
Predictive Delay Adjustment
t - Time - 20 ns/div
Figure 38. Predictive Gate Drive - G2 Falling
34
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UCC2540
SLUS539 - JUNE 2004
RELATED PRODUCTS D D D D D D
UCC28089 Primary Side Push-Pull Oscillator UCC27223 High Efficiency Predictive Synchronous Buck Driver with Enable UCC3583 Switch Mode Secondary Side Post Regulator UCC25701 Advanced Voltage Mode Pulse Width Modulator UCC3808A Low-Power Currrent-Mode Push-Pull PWM UCC38083/4/5/6 8-Pin Current-Mode Push-Pull PWM with Programmable Slope Compensation
REFERENCES
1. Power Supply Seminar SEM-1300 Topic 1: Unique Cascaded Power Converter Topology for High Current Low Output Voltage Applications, by L. Balogh, C. Bridge, and B. Andreycak, (SLUP118) 2. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by L. Balogh, (SLUP133) 3. Datasheet, UCC27223 High Efficiency Predictive Synchronous Buck Driver, (SLUS558) 4. Datasheet, UCC37323/4/5 Dual 4-A Peak High Speed Low-Side Power MOSFET Drivers, (SLUS492A) 5. Power Supply Seminar SEM1600 Topic 2: Sequencing Power Supplies in Multiple Voltage Rail Environments, by D. Daniels, D. Gehrke, and M. Segal, (SLUP224) 6. Technical Brief, PowerPAD Thermally Enhanced Package, (SLMA002) 7. Application Brief, PowerPAD Made Easy, (SLMA004) 8. Datasheet, TPS3103K33 Ultra-Low Supply Current/Supply Voltage Supervisory Circuits, (SLVS363) 9. Application Note, A Revolutionary Power Management Solution for Highly Efficient, Multiple Output Applications, by Bill Andreycak, (SLUA255) 10. Application Note, Predictive Gate DriveE FAQ, by Steve Mappus (SLUA285)
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35
UCC2540
SLUS539 - JUNE 2004
MECHANICAL DATA
PWP (R-PDSO-G**)
20 PINS SHOWN
PowerPAD PLASTIC SMALL-OUTLINE
0,65 20
0,30 0,19 11
0,10 M
Thermal Pad (See Notes D and F) 4,50 4,30 6,60 6,20 0,15 NOM
Gage Plane 1 A 10 0-8 0,25 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 PINS ** DIM A MAX A MIN 0,10
14 5,10 4,90
16 5,10 4,90
20 6,60 6,40
24 7,90 7,70
28 9,80 9,60 4073225/F 10/98
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 F. The PowerPADt is not directly connected any lead of the package. It is electrically and thermally connected to the substrate of the device which acts as ground. The exposed dimension is 1.3 mm x 1.7 mm. However, the tolerances can be +1.05 mm / -0.05 mm (+41 mils / -2 mils) due to position and mold flow variation.
Powe
36
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